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precision, selectable gain, fully differential funnel amplifier AD8475 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010C2011 analog devices, inc. all rights reserved. features precision attenuation: g = 0.4, g = 0.8 fully differential or single-ended input/output differential output designed to drive precision adcs drives switched capacitor and - adcs rail-to-rail output vocm pin adjusts output common mode robust overvoltage protection up to 15 v (v s = +5 v) single supply: 3 v to 10 v dual supplies: 1.5 v to 5 v high performance suited for driving 18-bit converter up to 4 msps 10 nv/hz output noise 3 ppm/c gain drift 500 v maximum output offset 50 v/s slew rate low power: 3.2 ma supply current applications adc drivers differential instrumentation amplifier building blocks single-ended-to-differential converters general description the AD8475 is a fully differential, attenuating amplifier with integrated precision gain resistors. it provides precision attenuation (by 0.4 or 0.8), common-mode level shifting, and single-ended-to- differential conversion along with input overvoltage protection. power dissipation on a single 5 v supply is only 16 mw. the AD8475 is a simple to use, fully integrated precision gain block, designed to process signal levels of up to 10 v on a single supply. it provides a complete interface to make industrial level signals directly compatible with the differential input ranges of low voltage high performance 16-bit or 18-bit single-supply successive approximation (sar) analog-to-digital converters (adcs). the AD8475 comes with two standard pin-selectable gain options: 0.4 and 0.8. the gain of the part is set by driving the input pin corresponding to the appropriate gain. the AD8475 also provides overvoltage protection from large industrial input voltages up to 15 v while operating on a single 5 v supply. the vocm pin adjusts the output voltage common mode for precision level shifting, to match the adcs input range and maximize dynamic range. functional block diagrams 12 11 10 1 3 4 nc ?out +out 9 vocm +in 0.4x ?in 0.8x 2 +in 0.8x ?in 0.4x 6 + v s 5 ? i n 0 . 4 x 7 + v s 8 + v s 1 6 + i n 0 . 4 x 1 5 ? v s 1 4 ? v s 1 3 ? v s 1k? 1.25k ? 1.25k ? 1k? AD8475 1.25k ? 1.25k ? nc = no connect 09432-001 figure 1. 16-lead lfcsp nc = no connect 1k ? 1k ? 1.25k ? 1.25k ? AD8475 ?in 0.8x 1 ?in 0.4x 2 +v s 3 vocm 4 +out 5 +in 0.8x 10 +in 0.4x 9 ?v s 8 nc 7 ?out 6 1.25k ? 1.25k ? 09432-002 figure 2. 10-lead msop the AD8475 works extremely well with sar, -, and pipeline converters. the high current output stage of the part allows it to drive the switched capacitor front-end circuits of many adcs with minimal error. unlike many differential drivers in the market, the AD8475 is a high precision amplifier. with 500 v maximum output offset, 10 nv/hz output noise, and ?112 db thd + n, the AD8475 pairs well with high accuracy converters. considering its low power consumption and high precision, the slew-enhanced AD8475 has excellent speed, settling to 18-bit precision for 4 msps acquisition. the AD8475 is available in a space-saving 16-lead 3 mm 3 mm lfcsp package and a 10-lead msop package. it is fully specified over the ?40c to +85c temperature range.
AD8475 rev. b | page 2 of 24 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description........................................................................... 1 ? functional block diagrams............................................................. 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? thermal resistance ...................................................................... 5 ? esd caution.................................................................................. 5 ? pin configurations and function descriptions ........................... 6 ? typical performance characteristics ............................................. 8 ? terminology .................................................................................... 16 ? theory of operation ...................................................................... 17 ? overview...................................................................................... 17 ? circuit information.................................................................... 17 ? dc precision ............................................................................... 17 ? input voltage range................................................................... 18 ? driving the AD8475................................................................... 18 ? power supplies ............................................................................ 18 ? applications information .............................................................. 19 ? typical configuration................................................................ 19 ? single-ended to differential conversion................................ 19 ? setting the output common-mode voltage .......................... 19 ? high performance adc driving ............................................. 20 ? AD8475 evaluation board ............................................................ 22 ? outline dimensions ....................................................................... 23 ? ordering guide .......................................................................... 24 ? revision history 4/11rev. a to rev. b added b grade columns to specifications section..................... 3 changes to figure 16........................................................................ 9 changes to figure 43...................................................................... 14 changes to ordering guide .......................................................... 24 1/11rev. 0 to rev. a added 16-lead lfcsp.................................................. throughout changes to table 1 and note 3........................................................ 3 change to table 2 ............................................................................. 5 added figure 3 and table 4; renumbered sequentially ............. 6 changes to typical performance characteristics format........... 8 added AD8475 evaluation board section and figure 56......... 22 10/10revision 0: initial version
AD8475 rev. b | page 3 of 24 specifications v s = 5 v, g = 0.4, vocm connected to 2.5 v, r l = 1 k differentially, t a = 25c, referred to output (rto), unless otherwise noted. table 1. b grade a grade parameter test conditions/comments min typ max min typ max unit dynamic performance ?3 db small signal bandwidth 150 150 mhz ?3 db large signal bandwidth 15 15 mhz slew rate 2 v step 50 50 v/s settling time to 0.01% 2 v st ep on output 45 45 ns settling time to 0.001% 2 v st ep on output 50 50 ns noise/distortion 1 thd + n f = 100 khz, v out = 4 v p-p, 22 khz band-pass filter ?112 ?112 db hd2 f = 1 mhz, v out = 2 v p-p ?110 ?110 db hd3 f = 1 mhz, v out = 2 v p-p ?96 ?96 db imd3 f 1 = 0.95 mhz, f 2 = 1.05 mhz, v out = 2 v p-p ?90 ?90 dbc imd3 f 1 = 95 khz, f 2 = 105 khz, v out = 2 v p-p ?84 ?84 dbc output voltage noise f = 0.1 hz to 10 hz 2.5 2.5 v p-p spectral noise density f = 1 khz 10 10 nv/hz gain 0.4 0.4 v/v gain error r l = 0.02 0.05 % gain drift ?40c t a +85c 1 3 1 3 ppm/c gain nonlinearity v out = 4 v p-p 2.5 2.5 ppm offset and cmrr offset 2 rto 50 200 50 500 v vs. temperature ?40c t a +85c 2.5 2.5 v/c vs. power supply v s = 2.5 v to 5 v 90 90 db common-mode rejection ratio v incm = 5 v 86 76 db input characteristics input voltage range 3 differential input ?6.25 +6.25 ?6.25 +6.25 v single-ended input ?12.5 +12.5 ?12.5 +12.5 v impedance 4 v incm = v s /2 single-ended input 2.92 2.92 k differential input 5 5 k common mode input 1.75 1.75 k output characteristics output swing ?v s + 0.05 +v s ? 0.05 ?v s + 0.05 +v s ? 0.05 output balance error ?v out,cm /?v out,dm 90 ?80 db output impedance 0.1 0.1 capacitive load per output 30 30 pf short-circuit current limit 110 110 ma vocm characteristics vocm input voltage range ?v s + 1 +v s ?v s + 1 +v s v vocm input impedance 100 100 k vocm gain error 0.02 0.02 %
AD8475 rev. b | page 4 of 24 b grade a grade parameter test conditions/comments min typ max min typ max unit power supply specified voltage 5 5 v operating voltage range 3 10 3 10 v supply current 3 3.2 3 3.2 ma over temperature ?40c t a +85c 4 4 ma temperature range specified performance range ?40 +85 ?40 +85 c operating range ?40 +125 ?40 +125 c 1 includes amplifier vo ltage and current noise, as well as noise of internal resistors. 2 includes input bias an d offset current errors. 3 the input voltage range is a function of the voltage supplies and esd diodes. 4 internal resistors are trimme d to be ratio matched but have 20% absolute accuracy.
AD8475 rev. b | page 5 of 24 absolute maximum ratings table 2. parameter rating supply voltage 11 v maximum voltage at any input pin +v s + 10.5 v minimum voltage at any input pin ?v s ? 16 v storage temperature range ?65c to +150c specified temperature range ?40c to +85c operating temperature range ?40c to +125c junction temperature 150c esd (ficdm) 1500 v esd (hbm) 2000 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 16-lead lfcsp (exposed pad) 84.90 c/w 10-lead msop 214.0 c/w esd caution
AD8475 rev. b | page 6 of 24 pin configurations and function descriptions 12 11 10 1 3 4 nc ?out +out 9 vocm +in 0.4x ?in 0.8x 2 +in 0.8x ?in 0.4x 6 + v s 5 ? i n 0 . 4 x 7 + v s 8 + v s 1 6 + i n 0 . 4 x 1 5 ? v s 1 4 ? v s 1 3 ? v s AD8475 top view (not to scale notes 1. nc = no connect. 2. solder the exposed paddle on the back of the package to a ground plane. 09432-003 figure 3. 16-lead lfcsp pin configuration table 4. 16-lead lfcsp pin function descriptions pin o. mnemonic description 1 +in 0.4x positive input for 0.4 attenuation. 2 +in 0.8x positive input for 0.8 attenuation 3 ?in 0.8x negative input for 0.8 attenuation. 4 ?in 0.4x negative input for 0.4 attenuation. 5 ?in 0.4x negative input for 0.4 attenuation. 6 +v s positive supply. 7 +v s positive supply. 8 +v s positive supply. 9 vocm output common-mode adjust. 10 +out positive output. 11 ?out negative output. 12 nc no connect. 13 ?v s negative supply. 14 ?v s negative supply. 15 ?v s negative supply. 16 +in 0.4x positive input for 0.4 attenuation. epad solder the exposed paddle on the ba ck of the package to a ground plane.
AD8475 rev. b | page 7 of 24 ?in 0.8x 1 ?in 0.4x 2 +v s 3 vocm 4 +out 5 +in 0.8x 10 +in 0.4x 9 ?v s 8 nc 7 ?out 6 AD8475 top view (not to scale nc = no connect 09432-004 figure 4. 10-lead msop pin configuration table 5. 10-lead msop pin function descriptions pin o. mnemonic description 1 ?in 0.8x negative input for 0.8 attenuation 2 ?in 0.4x negative input for 0.4 attenuation 3 +v s positive supply 4 vocm output common-mode adjust 5 +out noninverting output 6 ?out inverting output 7 nc no connect 8 ?v s negative supply 9 +in 0.4x positive input for 0.4 attenuation 10 +in 0.8x positive input for 0.8 attenuation
AD8475 rev. b | page 8 of 24 typical performance characteristics t a = 25c, v s = 5 v, gain = 0.4, r load = 1 k, rto, unless otherwise specified. 1000 ?1000 ?800 ?600 ?400 ?200 0 200 400 600 800 ?40 120 100 80 604020 0 ?20 v oso (v) temperature (c) g = 0.4 representative samples g = 0.8 09432-006 figure 5. system offset vs. temperature 5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 ?40 120 100 80 604020 0 ?20 cmrr (v/v) temperature (c) representative samples 09432-005 figure 6. cmrr vs. temperature (g = 0.8) 65 30 35 40 45 50 55 60 ?40 120 rise fall 1008060 4020 0 ?20 slew rate (v/s) temperature (c) 09432-015 figure 7. slew rate vs. temperature 10 ?8 ?6 ?4 ?2 0 2 4 6 8 ?5.5 ?4.5 ?3.5 ?2.5 ?1.5 ?0.5 0.5 1.5 2.5 3.5 4.5 5.5 common-mode voltage (v) output voltage (v) 09432-008 0v, +7.75v ?4.97v, +7.75v +4.95v, +7.75v 0v, +3.25v ?2.97v, +3.25v ?2.97v, ?3.75v +2.95v, +3.25v v s = +3v, vocm = +1.5v ?4.97v, ?6.25v 0v, ?6.25v 0v, ?3.75v +2.95v, ?3.75v +4.95v, ?6.25v v s = +5v, vocm = +2.5v figure 8. input common-mode voltage vs. output voltage, v s = +5 v and +3 v 150 ?150 ?100 ?50 0 50 100 ?40 120 1008060 4020 0 ?20 gain error (v/v) temperature (c) 09432-100 v in = 5v representative samples figure 9. gain error vs. temperature, v s = 5 v 130 80 85 90 95 100 105 110 115 120 125 ?40 120 100 80 604020 0 ?20 short-circuit current (ma) temperature (c) 09432-016 figure 10. short-circuit current vs. temperature
AD8475 rev. b | page 9 of 24 +v s 0.2 0.4 0.6 0.8 1.0 ?v s 0.2 0.4 0.6 0.8 1.0 100 1k 10k 100k 1m output voltage swing (v) referred to supply voltages r load ( ? ) ?40c +25c +85c +105c +125c 09432-013 figure 11. output voltage swing vs. r load vs. temperature, v s = 5 v and +5 v 2v/di v 100s/div 0.8 v in v out 09432-051 figure 12. overdrive recovery ? 20 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 100k 1m 10m psrr (db) frequency (hz) 09432-011 figure 13. power supply rejectio n ratio (psrr) vs. frequency +v s 0.2 0.4 0.6 0.8 1.0 ?v s 0.2 0.4 0.6 0.8 1.0 10a 100a 1ma 10ma 100ma output voltage swing (v) referred to supply voltages output current (a) ?40c +25c +85c +105c +125c 09432-014 figure 14. output voltage swing vs. output current vs. temperature, v s = 5 v and +5 v 10 0 1 2 3 4 5 6 7 8 9 100 10m 1m 100k 10k 1k maximum output voltage ( v p-p) frequency (hz) 09432-012 figure 15. maximum output voltage vs. frequency 100 20 30 40 50 60 70 80 90 10m 100m 1m 100k 10k 1k cmrr (db) frequency (hz) 09432-216 g = 0.8 g = 0.4 figure 16. cmrr vs. frequency
AD8475 rev. b | page 10 of 24 0 ?50 ?40 ?30 ?20 ?10 ?7.96 ?1.94 1k 1g 100m 10m 1m 100k 10k gain (db) frequency (hz) g = 0.8 g = 0.4 09432-017 figure 17. small signal frequency response for all gains v s = 5 v 0 ?40 ?30 ?20 ?10 ?7.96 1k 100m 10m 1m 100k 10k gain (db) frequency (hz) v s = 5v v s = +3v v s = +5v 09432-018 figure 18. small signal frequency response for various supplies ?50 ?20 ?30 ?40 0 ?10 100k 100m 10m 1m gain (db) frequency (hz) r l = 200 ? r l = 1k ? r l = 10k ? 09432-022 figure 19. small signal frequency response for various loads ?30 ?20 0 ?10 ?7.96 ?1.94 1k 100m 10m 1m 100k 10k gain (db) frequency (hz) g = 0.8 g = 0.4 09432-019 figure 20. large signal frequency response for all gains, v s = 5 v ?30 ?20 0 ?10 ?7.96 1k 100m 10m 1m 100k 10k gain (db) frequency (hz) v s = 5v v s = +3v v s = +5v 09432-020 figure 21. large signal frequenc y response for various supplies ?50 ?20 ?30 ?40 0 ?10 100k 100m 10m 1m gain (db) frequency (hz) r l = 200 ? r l = 1k ? r l = 10k ? 09432-024 figure 22. large signal frequency response for various loads
AD8475 rev. b | page 11 of 24 0 ?40 ?30 ?20 ?10 ?7.96 1k 100m 10m 1m 100k 10k gain (db) frequency (hz) c l = 0pf c l = 5pf c l = 10pf 09432-025 figure 23. small signal frequency response for various capacitive loads 0 ?40 ?30 ?20 ?10 10k 100m 10m 1m 100k gain (db) frequency (hz) vocm = 1v vocm = 2.5v vocm = 4v 09432-026 figure 24. small signal frequency response for various vocm levels ?2 ?15 5 ?10 ?5 0 1k 10m 1m 100k 10k vocm gain (db) frequency (hz) v out = 100mv p-p vocm = 2.5v 09432-056 figure 25. vocm small signal frequency response ?30 ?20 0 ?10 ?7.96 1k 100m 10m 1m 100k 10k gain (db) frequency (hz) c l = 0pf c l = 5pf c l = 10pf 09432-027 figure 26. large signal frequency response for various capacitive loads ?30 ?20 0 ?10 1k 100m 10m 1m 100k 10k gain (db) frequency (hz) vocm = 1.5v vocm = 2.5v vocm = 3.5v 09432-028 figure 27. large signal frequency response for various vocm levels ?40 ?30 10 ?20 ?10 0 1k 10m 1m 100k 10k vocm gain (db) frequency (hz) v out = 2v p-p vocm = 2.5v 09432-055 figure 28. vocm large signal frequency response
AD8475 rev. b | page 12 of 24 20mv/di v 10ns/div v out = 100mv p-p 09432-029 figure 29. small signal pulse response, v s = 2.5 v 20mv/di v 10ns/div c l = 0pf c l = 5pf c l = 10pf 09432-031 figure 30. small signal step response for various capacitive loads, v s = 2.5 v 20mv/div 10ns/div r l = 200 ? r l = 1k ? r l = 10k ? 09432-030 figure 31. small signal step resp onse for various resistive loads 500mv/di v 20ns/div v out = 2v p-p 09432-033 figure 32. large signal pulse response, v s = 2.5 v 500mv/di v 20ns/div c l = 0pf c l = 5pf c l = 10pf 09432-035 figure 33. large signal step response for various capacitive loads 500mv/div 20ns/div r l = 200 ? r l = 1k ? r l = 10k ? 09432-034 figure 34. large signal step response for various resistive loads
AD8475 rev. b | page 13 of 24 20mv/di v 50ns/div 09432-032 figure 35. vocm small signal step response, v s = 2.5 v ? 20 ?140 ?120 ?100 ?80 ?60 ?40 0.1 1 10 harmonic distortion (dbc) frequency (mhz) hd2, g = 0.4 hd3, g = 0.4 hd2, g = 0.8 hd3, g = 0.8 09432-043 figure 36. harmonic distortion vs. frequency at various gains ? 20 ?140 ?120 ?100 ?80 ?60 ?40 0.1 1 10 harmonic distortion (dbc) frequency (mhz) hd2, r l = 1k ? hd3, r l = 1k ? hd2, r l = 200 ? hd3, r l = 200 ? v out = 2v p-p 09432-040 figure 37. harmonic distortion vs. frequency at various loads 500mv/di v 500ns/div 09432-036 figure 38. vocm large signal step response ? 20 ?140 ?120 ?100 ?80 ?60 ?40 0.1 1 10 harmonic distortion (dbc) frequency (mhz) hd2, v s = +5v hd3, v s = +5v hd2, v s = 5v hd3, v s = 5v v out = 2v p-p 09432-042 figure 39. harmonic distortion vs. frequency at various supplies ? 20 ?140 ?120 ?100 ?80 ?60 ?40 0.1 1 10 harmonic distortion (dbc) frequency (mhz) hd2, v out = 2v p-p hd3, v out = 2v p-p hd2, v out = 4v p-p hd3, v out = 4v p-p 09432-046 figure 40. harmonic distortion vs. frequency at various v out,dm
AD8475 rev. b | page 14 of 24 ? 20 ?140 ?120 ?100 ?80 ?60 ?40 09 87654321 harmonic distortion (dbc) v out (v p-p) hd2, +5v supply hd3, +5v supply hd2, 5v supply hd3, 5v supply f = 100khz 09432-047 figure 41. harmonic distortion vs. v out at various supplies ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 75 80 85 90 95 100 105 110 115 120 125 normalized spectrum (dbc) frequency (khz) 09432-054 figure 42. 100 khz intermodulation distortion 100 20 10 0 30 40 50 60 70 80 90 10k 100k 1k 100 10 1 voltage noise (nv/ hz) frequency (hz) 09432-243 figure 43. voltage noise density vs. frequency ? 20 ?140 ?120 ?100 ?80 ?60 ?40 0.1 1 10 spurious-free dyanmic range (dbc) frequency (mhz) r l = 1k ? r l = 200 ? v out = 2v p-p 09432-049 figure 44. spurious-free dynamic range vs. frequency at various loads 100 0.01 0.1 1 10 10k 100k 1m 10m 100m output impedance ( ? ) frequency (hz) 09432-052 figure 45. output impe dance vs. frequency 500nv/di v 1s/div 09432-039 figure 46. 0.1 hz to 10 hz voltage noise
AD8475 rev. b | page 15 of 24 ? 30 ?100 ?80 ?90 ?70 ?60 ?50 ?40 1m 10m 100m output balance error (db) frequency (hz) 09432-050 figure 47. output balanc e error vs. frequency
AD8475 rev. b | page 16 of 24 terminology +in v ocm ?in +out ?out v out, dm r l, dm AD8475 1k ? 1.25k ? 1.25k ? 1k ? 09432-162 figure 48. signal and circuit definitions differential voltage differential voltage refers to the difference between two node voltages. for example, the output differential voltage (or equivalently, output differential mode voltage) is defined as v out, dm = ( v +out ? v ?out ) where v +out and v ?out refer to the voltages at the +out and ?out terminals with respect to a common ground reference. similarly, the differential input voltage is defined as v in, dm = ( v +in ? (v ?in )) common-mode voltage common-mode voltage refers to the average of two node voltages with respect to the local ground reference. the output common- mode voltage is defined as v out, cm = ( v +out + v ?out )/2 balance output balance is a measure of how close the output differential signals are to being equal in amplitude and opposite in phase. output balance is most easily determined by placing a well- matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider midpoint with the magnitude of the differential signal. by this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential mode voltage. dmout cmout v v error balance output , , =
AD8475 rev. b | page 17 of 24 theory of operation overview the AD8475 is a fully differential amplifier, with integrated laser- trimmed resistors, that provides precision attenuating gains of 0.4 and 0.8. the internal differential amplifier of the AD8475 differs from conventional operational amplifiers in that it has two outputs whose voltages are equal in magnitude, but move in opposite directions (180 out of phase). an additional input, vocm, sets the output common-mode voltage. like an opera- tional amplifier, it relies on high open-loop gain and negative feedback to force the output nodes to the desired voltages. the AD8475 is designed to greatly simplify single-ended-to-differential conversion, common-mode level shifting and precision attenua- tion of large signals so that they are compatible with low voltage, differential input adcs. 0 9432-062 1k ? 1k ? 1.25k ? 1.25k ? AD8475 ? in 0.8x ?in 0.4x +v s vocm +out +in 0.8x +in 0.4x ?v s nc ? ou t 1.25k ? 1.25k ? figure 49. block diagram circuit information the AD8475 amplifier uses a voltage feedback topology; therefore, the amplifier exhibits a nominally constant gain bandwidth product. like a voltage feedback operational amplifier, the AD8475 also has high input impedance at its internal input terminals (the summing nodes of the internal amplifier) and low output impedance. the AD8475 employs two feedback loops, one each to control the differential and common-mode output voltages. the differen- tial feedback loop, which is fixed with precision laser trimmed on-chip resistors, controls the differential output voltage. output common-mode voltage (vocm) the internal common-mode feedback controls the common- mode output voltage. this architecture makes it easy to set the output common-mode level to any arbitrary value independent of the input voltage. the output common-mode voltage is forced by the internal common-mode feedback loop to be equal to the voltage applied to the vocm input. the vocm pin can be left unconnected, and the output common-mode voltage self-biases to midsupply by the internal feedback control. due to the internal common-mode feedback loop and the fully differential topology of the amplifier, the AD8475 outputs are precisely balanced over a wide frequency range. this means that the amplifiers differential outputs are very close to the ideal of being identical in amplitude and exactly 180 out of phase. dc precision the dc precision of the AD8475 is highly dependent on the accuracy of its internal resistors. using superposition to analyze the circuit shown in figure 50 , the following equation shows the relationship between the input and output voltages of the amplifier: () () () () ++ +? = ++ +? 2 2 1 2 2 1 , , , , where, rg p rfp r p = , rg n rfn r n = np dmin vvv ? = , )( 2 1 , np cmin vv v += the differential closed loop gain of the amplifier is np npnp dmin dmout rr rrrr v v ++ ++ = 2 2 , , and the common rejection of the amplifier is ( ) ++ ? = 2 2 , , 09432-163 rfp rfn rgp rgn v on v op vocm v p v n figure 50. functional circuit diagram of the AD8475 at a given gain the preceding equations show that the gain accuracy and the common-mode rejection (cmrr) of the AD8475 are deter- mined primarily by the matching of the feedback networks (resistor ratios). if the two networks are perfectly matched, that is, if r p and r n equal rf/rg, then the resistor network does not generate any cmrr errors and the differential closed loop gain of the amplifier reduces to rg rf v v dmin dmout = , , the AD8475s integrated resistors are precision wafer-laser- trimmed to guarantee a mini mum cmrr of 86db (50v/v), and gain error of less that 0.05%. to achieve equivalent precision and performance using a discrete solution, resistors must be matched to 0.01% or better.
AD8475 rev. b | page 18 of 24 input voltage range the AD8475 can measure input voltages that are larger than the supply rails. the internal gain and feedback resistors form a divider, which reduces the input voltage seen by the internal input nodes of the amplifier. the largest voltage that can be measured is constrained by the capability of the amplifiers internal summing nodes. this voltage is defined by the input voltage and the ratio between the feedback and the gain resistors. figure 51 shows the voltage at the internal summing nodes of the amplifier, defined by the input voltage and internal resistor network. if v n is grounded, the expression shown in the figure reduces to ? ? ? ? ? ? + + == p minus plus v rg rf vocm rgrf rg vv 2 1 the internal amplifier of the AD8475 has rail-to-rail inputs. to obtain accurate measurements with minimal distortion, the voltage at the internal inputs of the amplifier must stay below +v s ? 1 v and above ?v s . for example, with v s = 5 v in a g = 0.4 configuration, the AD8475 can measure an input as high as 12.5 v and maintain its excellent distortion performance. the AD8475 provides overvoltage protection for excessive input voltages beyond the supply rails. integrated esd protection diodes at the inputs prevent damage to the AD8475 up to +v s + 10.5 v and ?v s ? 16 v. driving the AD8475 care should be taken to drive the AD8475 with a low impedance source: for example, another amplifier. source resistance can unbalance the resistor ratios and, therefore, significantly degrade the gain accuracy and common-mode rejection of the AD8475. for the best performance, source impedance to the AD8475 input terminals should be kept below 0.1 . refer to the dc precision section for details on the critical role of resistor ratios in the precision of the AD8475. power supplies the AD8475 operates over a wide range of supply voltages. it can be powered on a single supply as low as 3 v and as high as 10 v. the AD8475 can also operate on dual supplies from 1.5 v up to 5 v a stable dc voltage should be used to power the AD8475. note that noise on the supply pins can adversely affect performance. for more information, see the psrr performance curve in figure 13 . place a bypass capacitor of 0.1 f between each supply pin and ground, as close as possible to each supply pin. use a tantalum capacitor of 10 f between each supply and ground. it can be farther away from the supply pins and, typically, it can be shared by other precision integrated circuits. rf rf rg rg v on v op vocm v p v n v n rf + rg rf v p ? v n rg rf vocm rf + rg rg + + 2 1 09432-164 figure 51. voltages at the internal op amp inputs of the AD8475
AD8475 rev. b | page 19 of 24 applications information typical configuration the AD8475 is designed to facilitate single-ended-to-differential conversion, common-mode level shifting, and precision attenuation of large signals so that they are compatible with low voltage adcs. figure 53 shows a typical connection diagram of the AD8475 in a gain of 0.4. to use the AD8475 in a gain of 0.8, drive the in 0.8x inputs with a low impedance source. single-ended to differential conversion many industrial systems use single-ended; however, the signals are frequently processed by high performance differential input adcs for higher precision. the AD8475 performs the critical function of precisely converting single-ended signals to the differential inputs of precision adcs, and it does so with no need for external components. to convert a single-ended signal to a differential signal, connect one input to the signal source and the other input to ground (see figure 55 ). note that either input can be driven by the source with the only effect being that the outputs have reversed polarity. the AD8475 also accepts truly differential input signals in precision systems with differential signal paths. setting the output common-mode voltage the vocm pin of the AD8475 is internally biased with a precision voltage divider comprising two 200 k resistors between the supplies. this divider level shifts the output to midsupply. relying on the internal bias results in an output common-mode voltage that is within 0.01% of the expected value. in cases where control of the output common-mode level is desired, an external source or resistor divider with source resistance less than 100 can be used to drive the vocm pin. if an external voltage divider consisting of equal resistor values is used to set vocm to midsupply, higher values can be used because the external resistors are placed in parallel with the internal resistors. the output common-mode offset listed in the specifications section assumes that the vocm input is driven by a low impedance voltage source. because of the internal divider, the vocm pin sources and sinks current, depending on the externally applied voltage and its associated source resistance. it is also possible to connect the vocm input to the common- mode level output of an adc; however, care must be taken to ensure that the output has sufficient drive capability. the input impedance of the vocm pin is 100 k. if multiple AD8475 devices share one adc reference output, a buffer may be neces- sary to drive the parallel inputs. 09432-200 v out = (v +out ? v ?out ) 0.1f ref +v s + 0.1f 10f low impedance input source ?v s + 0.1f 10f 1k? 1k? 1.25k ? 1.25k ? AD8475 ?in 0.8x ?in 0.4x +v s vocm +out +in 0.8x +in 0.4x ?v s nc ?out 1.25k ? 1.25k ? figure 52. typical configuration10-lead msop
AD8475 rev. b | page 20 of 24 12 11 10 1 3 4 nc ?out +out 9 vocm +in 0.4x ?in 0.8x 2 +in 0.8x ?in 0.4x 6 + v s 5 7 + v s 8 + v s 1 6 + i n 0 . 4 x 1 5 ? v s 1 4 ? v s 1 3 ? v s 1k ? 1.25k ? 1.25k ? 1k ? AD8475 1.25k ? 1.25k ? ? i n 0 . 4 x +v s ?v s 0.1f v out = (v +out ? v ?out ) ref + 0.1f 10f low impedance input source v in + 0.1f 10f 09432-165 figure 53. typical configuration16-lead lfcsp high performance adc driving the AD8475 is ideally suited for broadband dc-coupled and industrial applications. the circuit in figure 55 shows an industrial front-end connection for an AD8475 driving an ad7982 , a 18-bit, 1 msps adc, with dc coupling on the AD8475 input and output. (the ad7982 achieves its optimum performance when driven differentially.) the AD8475 performs the attenuation of a 20 v p-p input signal, level shifts it, and converts it to a differential signal without the need for any external components. the AD8475 eliminates the need for dual supplies at the front end to accept large bipolar signals. it also eliminates the need for a precision resistor network for attenua- tion, and a transformer to drive the adc and perform the single- ended-to-differential conversion. the ac and dc performance of the AD8475 are compatible with the 18-bit, 1 msps ad7982 pulsar? adc and other 16-bit and 18-bit members of the family, which have sampling rates up to 4 msps. some suitable high performance differential adcs are listed in table 6 . table 6. high performance sar adcs part resolution sample rate description ad7984 18 bits 1.33 msps true differential input, 14 mw, 2.5 v adc ad7982 18 bits 1 msps true differential input, 7.0 mw, 2.5 v adc ad7690 18 bits 400 ksps true differential input, 4.5 mw, 5 v adc ad7641 18 bits 2 msps true differential input, 75 mw, 2.5 v adc in this example, the AD8475 is powered with a single 5 v supply and used in a gain of 0.4, with a single-ended input converted to a differential output. the input is a 20 v p-p symmetric, ground-referenced bipolar signal. with an output common-mode voltage of 2.5 v, each AD8475 output swings between 0.5 v and 4.5 v, opposite in phase, providing an 8 v p-p differential signal to the adc input.
AD8475 rev. b | page 21 of 24 the differential rc network between the AD8475 output and the adc provides a single-pole filter that reduces undesirable aliasing effects and high frequency noise. the common-mode bandwidth of the filter is 29.5 mhz (20 , 270 pf), and the differential bandwidth is 3.1 mhz (40 , 1.3 nf). the vocm input is bypassed for noise reduction, and set externally with 1% resistors to maximize output dynamic range on a single 5 v supply. 09432-168 figure 54. fft results of the AD8475 driving the ad7982 ad7982 AD8475 20v ?10v 0v +10v +7v to +18v +0.5v +2.5v +4.5 v nc nc +in 0.4x ?in 0.4x +in 0.8x ?in 0.8x 4v +0.5v 2.5v +4.5v 4v ?out in? in+ +out vocm +v s +5v ?v s adr435 20? 20? 270pf 270pf 1.3nf vio cnv gnd ref vdd sdo sck sdi +5v +2.5v +1.8v to +5v 10k ? 10k? 0.1f +5v 09432-167 figure 55. attenuation and level shifting of industrial voltages to drive single-supply precision adc
AD8475 rev. b | page 22 of 24 AD8475 evaluation board an evaluation board for the AD8475 is available to facilitate standalone testing of the AD8475 performance and functionality for customer evaluation and system design. the board provides the user flexibility to configure the AD8475 in the desired gain (0.4 or 0.8) and to install the suitable input and load impedances. the AD8475-evalz board is designed so that a user can easily evaluate system performance when the AD8475 is mated with any analog devices, inc., sar adc. the board can be installed with smb connectors that mate directly to the pulsar? analog- to-digital converter evaluation kit . see the AD8475 product page for more information on the AD8475-evalz. + v 12 11 10 1 3 4 nc ?out +out 9 vocm +in 0.4x ?in 0.8x 2 +in 0.8x ?in 0.4x 6 + v s 5 7 + v s 8 + v s 1 6 + i n 0 . 4 x 1 5 ? v s 1 4 ? v s 1 3 ? v s 1k ? 1.25k ? 1.25k ? 1k ? AD8475 1.25k ? 1.25k ? r7 r8 r2 0 ? r1 0 ? r3 0 ? r4 0 ? in+ j1 r5 in? j2 r6 ? i n 0 . 4 x + c1 0.1f c3 10f + c4 10f c2 0.1f s (grn) out? j4 r9 r12 jp1 out+ j5 r10 vocm j3 vocm 09432-065 c5 0.1f r11 +v s (red) figure 56. AD8475-evalz schematic
AD8475 rev. b | page 23 of 24 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.65 1.50 sq 1.45 091609-a 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.80 0.75 0.70 compliant to jedec standards mo-229. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 57. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-27) dimensions shown in millimeters compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 10 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 58. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters
AD8475 rev. b | page 24 of 24 ordering guide model 1 temperature range package description package option branding AD8475acpz-r7 ?40c to +85c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-27 y3h AD8475acpz-rl ?40c to +85c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-27 y3h AD8475acpz-wp ?40c to +85c 16-lead lead frame chip scale package [lfcsp_wq] cp-16-27 y3h AD8475brmz ?40c to +85c 10-lead lead frame chip scale package [msop] rm-10 y41 AD8475brmz-r7 ?40c to +85c 10-lead lead frame chip scale package [msop] rm-10 y41 AD8475brmz-rl ?40c to +85c 10-lead lead frame chip scale package [msop] rm-10 y41 AD8475armz ?40c to +85c 10-lead lead frame chip scale package [msop] rm-10 y31 AD8475armz-r7 ?40c to +85c 10-lead lead frame chip scale package [msop] rm-10 y31 AD8475armz-rl ?40c to +85c 10-lead lead frame chip scale package [msop] rm-10 y31 AD8475-evalz evaluation board 1 z = rohs compliant part. ?2010C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09432-0-4/11(b)

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